(1) Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a flag register for use in such as interrupt controllers and timers, which has a bit clear and a register initialization function.
(2) Description of the Related Art
Microcomputers are used in a wide range of fields, and the diversification of their functions and the improvement of their performance are being steadily advanced. It is desirable to make the occupied area of the unit on the semiconductor substrate and the number of transistors as small as possible, thereby reducing the price of such microcomputers.
Various kinds of flag registers are needed in the microcomputer to memorize the interrupt status and the interrupt control. Data memory cells are arranged in arrays in the flag register, and the flag register is generally provided with signal lines which perform the reading and writing of the data (hereinafter called "R/W data lines"), address lines each of which specifies a specific cell, a control unit which controls the data reading and the data writing (hereinafter called "R/W control unit"), and cell clear lines which perform the data clear.
FIGS. 1A and 1B show such conventional flag register to which the present invention relates and which is used in the interrupt controller.
A flag register 001 shown in FIG. 1A comprises: an R/W control unit 020 which controls the data read and the data write, and eight sets of registers such as a register 010 which indicates the interrupt receive status (hereinafter called "IF register"), a register 011 which indicates the enable or disable of the interrupt receiving (hereinafter called "MK register"), and a register 017 which indicates the interrupt processing method (hereinafter called "CS register"). Each of the registers has eight memory cells that memorize the data corresponding to the eight types of interrupt causes. To these registers, a plurality of address signals 210.about.217 are inputted to specify a register which is subjected to the data read and the data write. Also, a plurality of cell clear signals 220.about.227 and a plurality of select signals 200.about.207 are inputted to specify the cells from which the data are to be cleared. The R/W control unit 020 has input terminals 250.about.257 for inputting the data and output terminals 240.about.247 for outputting the data. The R/W control circuit 020 also receives a write enable signal 230 which indicates data write permission.
Next, the detailed structure of one of the cells of the flag register 001 and a part 021 of the R/W control unit 020 of FIG. 1A is shown in FIG. 1B. The cell 100 comprises: a latch 300 which memorizes the data and which is formed by two inverters 301 and 302 each for inverting the logic value of the data; two transistors 303 and 304 which are used for the data read and the data write; and two transistors 305 and 306 which are used for the data clear. In the cell, the data is memorized in an output line 322 of the inverter 302, and its inverted data is memorized in an output line 321 of the inverter 301. The output lines 322 and 321 are connected through the transistor 303 to the R/W data line Q 310, and through the transistor 304 to the R/W data line Q 311, respectively. The transistors 303 and 304 perform connection and disconnection of the latch 300 to the R/W data lines 310 and 311 in such a way that, when the signal of the address line 313 is "1", they perform a connection, and when the same is "0", they perform a disconnection. The R/W data lines 310 and 311 are connected to clocked buffers 307 and 308 which are controlled by the write enable signal 230. An input terminal of the clocked buffer 307 is connected directly to the input terminal, and that of the clocked buffer 308 is connected through an inverter 309 to the data input terminal 250. Also, the R/W data line Q 310 is connected directly to the data output terminal 240.
The actual operation of the flag register 001 shown in FIG. 1A is explained below with reference to FIG. 1B. In the case of reading-out of the data, the selection of one of the registers can be effected by making one of the address signals 210.about.217 "1" and the rest of the address signals "0" and, thus, the data stored in the selected register are read out simultaneously from the output terminals 240.about.247. In the case of writing of the data, a register can be selected using the address signals 210.about.217, and setting the write enable signal 230 to "1". With the write enable signal 230 being set to "1", the clocked buffers 307 and 308 are operated so as to output the input data to the R/W data line Q 310 and to output the input data inverted by the inverter 309 to the R/W data line Q 311, whereby the data stored in the register are renewed (written over) at the same time. In the case of clearing of the data, the register(s) can be specified by setting the level of the cell clear signal(s) 220.about.227 to "1", and the bit(s) can be specified by setting the level of the select signal(s) 200.about.207 to "1". In the cells in which the levels of both the cell clear signal and the select signal are "1", because the transistors 305 and 308 connected in series become conductive, the potential at the output line 322 of the inverter 302 assumes the same potential as the ground level that is at a logic level "0", whereby the data of the cell is cleared to "0". In the case of initializing of the data, one register is selected by the address signals 210.about.217 in the same manner as in the data writing operation, and the initial data are written therein, thereby completing the initialization of the particular one register. By selecting all of the registers in succession using the address signals 210.about.217, and performing a similar operation, the initialization of all the registers can be completed.
In the conventional flag register as explained above, two R/W data lines, an address line, a cell clear signal line, and a select signal line must be provided for each cell. Also, each of the cells requires a circuit for cell clear or cell initialize operations. In this kind of circuit configuration, the realization of the flag register with a small amount of hardware area was difficult. This is a problem to be solved by the invention in the conventional flag register.